1. Field of the Invention
The present invention relates generally to methods for forming patterned planarized aperture fill layers within apertures within topographic substrate layers employed within microelectronics fabrications. More particularly, the present invention relates to high density plasma chemical vapor deposition (HDP-CVD) methods in conjunction with chemical mechanical polish (CMP) planarizing methods for forming patterned planarized aperture fill layers within apertures within topographic substrate layers employed within microelectronics fabrications.
2. Description of the Related Art
Semiconductor integrated circuit microelectronics fabrications are formed from semiconductor substrates within and upon whose surfaces are formed semiconductor integrated circuit devices. The semiconductor integrated circuit devices are connected internally and externally to the semiconductor substrates upon which they are formed through use of patterned conductor layers which are separated by dielectric layers.
As semiconductor integrated circuit microelectronics fabrication integration levels have increased and semiconductor integrated circuit device and patterned conductor layer dimensions have decreased, it has become more prevalent in the art of semiconductor integrated circuit microelectronics fabrication to employ trench isolation methods, such as but not limited to shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods, to form patterned planarized trench isolation regions within isolation trenches within semiconductor substrates in order to separate active regions of the semiconductor substrates within and upon which are formed semiconductor integrated circuit devices.
Such shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods are desirable for forming patterned planarized trench isolation regions within isolation trenches within semiconductor substrates employed within semiconductor integrated circuit microelectronics fabrications since shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods typically provide patterned planarized trench isolation regions which are nominally co-planar with the surfaces of adjoining active regions of a semiconductor substrate which they separate. Such nominally co-planar patterned planarized trench isolation regions and adjoining active regions of a semiconductor substrate generally optimize an attenuated depth of focus typically achievable with an advanced photoexposure apparatus employed when forming advanced semiconductor integrated circuit devices and patterned conductor layers within an advanced semiconductor integrated circuit microelectronics fabrication.
Of the methods which may be employed for forming patterned planarized shallow trench isolation (STI) regions within semiconductor substrates employed within semiconductor integrated circuit microelectronics fabrications, high density plasma chemical vapor deposition (HDP-CVD) methods employed in conjunction with chemical mechanical polish (CMP) planarizing methods have recently received considerable attention. High density plasma chemical vapor deposition (HDP-CVD) methods are typically characterized as, and alternately known as, simultaneous chemical vapor deposition (CVD) and inert gas ion sputter (typically argon ion sputter) methods, where a deposition rate within the chemical vapor deposition (CVD) method exceeds a sputtering rate within the inert gas ion sputtering method.
While high density plasma chemical vapor deposition (HDP-CVD) methods undertaken in conjunction with chemical mechanical polish (CMP) planarizing methods are thus desirable within the art of semiconductor integrated circuit microelectronics fabrication for forming patterned planarized trench isolation regions within isolation trenches within semiconductor substrates employed within advanced semiconductor integrated circuit microelectronics fabrications, patterned planarized trench isolation regions are often not formed entirely without problems within semiconductor integrated circuit microelectronics fabrications while employing high density plasma chemical vapor deposition (HDP-CVD) methods in conjunction with chemical mechanical polish (CMP) planarizing methods. In particular, it is often difficult to form with optimal uniformity and planarity, and with attenuated semiconductor substrate damage, a series of patterned planarized trench isolation regions within a series of isolation trenches separated by a series of mesas of varying width but substantially equivalent height within a semiconductor substrate while employing a high density plasma chemical vapor deposition (HDP-CVD) method in conjunction with a chemical mechanical polish (CMP) planarizing method as is conventional in the art of semiconductor integrated circuit microelectronics fabrication.
It is thus towards the goal of forming within a semiconductor integrated circuit microelectronics fabrication with optimal uniformity and planarity and with attenuated semiconductor substrate damage a series of patterned planarized trench isolation regions within a series of isolation trenches separated by a series of mesas of varying width while employing a high density plasma chemical vapor deposition (HDP-CVD) method in conjunction with a chemical mechanical polish (CMP) planarizing method, that the present invention is more specifically directed. In a more general sense, the present invention is also directed towards providing a method for forming within a microelectronics fabrication which need not necessarily be a semiconductor integrated circuit microelectronics fabrication, with optimal uniformity and planarity and with attenuated microelectronics substrate damage, a series of patterned planarized aperture fill layers within a series of apertures separated by a series of mesas of varying width, while employing a high density plasma chemical vapor deposition (HDP-CVD) method in conjunction with a chemical mechanical polish (CMP) planarizing method.
Various methods have been disclosed in the art of microelectronics fabrication for forming planarized aperture fill layers within apertures within topographic substrate layers employed within microelectronics fabrications.
For example, Nag et al., in xe2x80x9cComparative Evaluation of Gap-Fill Dielectrics in Shallow Trench Isolation for Sub-0.25 xcexcm Technologies,xe2x80x9d IEDM 96, IEEE, pp. 841-44, compares a series of physical and electrical properties for each of several dielectric materials formed employing several corresponding deposition methods which may be employed in conjunction with chemical mechanical polish (CMP) planarizing methods for forming patterned planarized trench isolation regions within isolation trenches within semiconductor substrates employed within semiconductor integrated circuit microelectronics fabrications.
In addition, Avanzino et al., in U.S. Pat. No. 4,954,459, discloses a polishing planarizing method for forming a planarized aperture fill dielectric layer within an aperture, such as but not limited to an isolation trench, within a topographic substrate layer, such as but not limited to a semiconductor substrate, employed within a semiconductor integrated circuit microelectronics fabrication. The method employs a conformal dielectric oxide layer formed over the topographic substrate layer, where upper lying portions of the conformal dielectric oxide layer corresponding with upper lying features of an underlying topography of the topographic substrate layer are selectively etched prior to a polish planarizing of the etched conformal dielectric oxide layer so formed.
Further, Sato, in U.S. Pat. No. 5,182,221, discloses an electron cyclotron resonance chemical vapor deposition (ECR-CVD) method for forming a void free planarized aperture fill layer within an aperture within a topographic substrate layer employed within a microelectronics fabrication, where the void free planarized aperture fill layer is formed without increasing an aspect ratio of the aperture into which is formed the void free planarized aperture fill layer. The method realizes the foregoing result by employing within the method a deposition rate ratio for vertical surface deposition of the void free planarized aperture fill layer with respect to horizontal surface deposition of the void free planarized aperture fill layer equal to twice the depth of the aperture into which is formed the void free planarized aperture fill layer divided by the width of the aperture into which is formed the void free planarized aperture fill layer.
Yet further, Grewal et al., in U.S. Pat. No. 5,212,114, discloses a non-polishing planarizing method for forming a planarized aperture fill layer filling a series of apertures within a topographic substrate layer formed within a microelectronics fabrication. The method employs a patterned photoresist etch stop layer formed interposed between a conformal dielectric layer formed upon the topographic substrate layer and a sacrificial planarizing layer formed over the topographic substrate layer, where the sacrificial planarizing layer and upper lying portions of the conformal dielectric layer are etched back employing an anisotropic etch method prior to stripping from the topographic substrate layer the patterned photoresist layer and forming over the topographic substrate layer a second dielectric layer.
Still further, Bose et al., in U.S. Pat. No. 5,492,858, discloses a polish planarizing method for forming a planarized trench isolation region within an isolation trench of high aspect ratio within a semiconductor substrate employed within a semiconductor integrated circuit microelectronics fabrication. The method employs forming a silicon nitride trench liner layer within the isolation trench prior forming within the isolation trench a conformal oxide dielectric layer which is subsequently steam annealed and polish planarized to form the planarized trench isolation region exhibiting enhanced properties.
Still yet further, Jain, in U.S. Pat. No. 5,494,854, discloses a chemical mechanical polish (CMP) planarizing method for planarizing a dielectric layer formed over a series of patterned conductor layers of equivalent thickness, but differing aspect ratios, formed within a microelectronics fabrication. The method employs forming a first gap filling dielectric layer for planarizing apertures formed interposed between at least the patterns which comprise a high aspect ratio portion of the patterned conductor layers, where the first gap filling dielectric layer has formed thereupon a second dielectric layer which is chemical mechanical polish (CMP) planarized with enhanced throughput, planarity and uniformity.
Finally, Gocho et al., in U.S. Pat. No. 5,498,565, discloses a high density plasma chemical vapor deposition (HDP-CVD) method in conjunction with a chemical mechanical polish (CMP) planarizing method for forming a series of patterned planarized trench isolation regions within a series of isolation trenches separated by a series of mesas of varying width within a semiconductor integrated circuit microelectronics fabrication. The method employs a masked isotropic etching of a portion of a comparatively thicker portion of a high density plasma chemical vapor deposited (HDP-CVD) dielectric layer formed upon a wider mesa within the series of mesas prior to chemical mechanical polish (CMP) planarizing the high density plasma chemical vapor deposited (HDP-CVD) dielectric layer.
Desirable within the art of microelectronics fabrication are additional high density plasma chemical vapor deposition (HDP-CVD) methods employed in conjunction with chemical mechanical polish (CMP) planarizing methods which may be employed for forming within a microelectronics fabrication with optimal uniformity and planarity and with attenuated microelectronics substrate damage a series of patterned planarized aperture fill layers within a series of apertures separated by a series of mesas of varying width. More particularly desirable within the art of semiconductor integrated circuit microelectronics fabrication are additional high density plasma chemical vapor deposition (HDP-CVD) methods employed in conjunction with chemical mechanical polish (CMP) planarizing methods which may be employed for forming within a semiconductor substrate with optimal uniformity and planarity and with attenuated semiconductor substrate damage a series of patterned planarized trench isolation regions within a series of isolation trenches separated by a series of mesas of varying width.
It is towards the foregoing goals that the present invention is both generally and more specifically directed.
A first object of the present invention is to provide high density plasma chemical vapor deposition (HDP-CVD) method employed in conjunction with a chemical mechanical polish (CMP) planarizing method for forming within a topographic substrate layer employed within a microelectronics fabrication a series of patterned planarized aperture fill layers.
A second object of the present invention is to provide a method in accord with the first object of the present invention, where the series of patterned planarized aperture fill layers is formed with optimal uniformity and planarity and with attenuated topographic substrate layer damage.
A third object of the present invention is to provide a method in accord with the first object of the present invention or the second object of the present invention, where the microelectronics fabrication is a semiconductor integrated circuit microelectronics fabrication, the topographic substrate layer is a semiconductor substrate employed within the semiconductor integrated circuit microelectronics fabrication, the series of apertures is a series of isolation trenches formed within the semiconductor substrate and the series of patterned planarized aperture fill layers is a series of patterned planarized trench isolation regions formed within the series of isolation trenches.
A fourth object of the present invention is to provide a method in accord with the first object of the present invention, the second object of the present invention or the third object of the present invention, which method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a chemical mechanical polish (CMP) planarizing method for forming a series of patterned planarized aperture fill layers within a series of apertures within a topographic substrate layer employed within a microelectronics fabrication. To practice the method of the present invention, there is first provided a topographic substrate layer employed within a microelectronics fabrication. The topographic substrate layer comprises a series of mesas of substantially equivalent height but of differing widths, where the series of mesas is separated by a series of apertures. There is then formed upon the topographic substrate layer a blanket first aperture fill layer. The blanket first aperture fill layer is formed employing a simultaneous deposition and sputter method, where the blanket first aperture fill layer fills the series of apertures to a planarizing thickness at least as high as the height of the mesas while simultaneously forming a series of protrusions of the blanket first aperture fill layer corresponding with the series of mesas. The thickness of a protrusion of the blanket first aperture fill layer over a narrow mesa is less than the thickness of a protrusion of the blanket first aperture fill layer over a wide mesa. The deposition and sputter method employs a deposition rate:sputter rate ratio which provides sufficient thickness of the blanket first aperture fill layer over the narrow mesa such that upon chemical mechanical polish (CMP) planarity the blanket first aperture fill layer to form a series of patterned planarized first aperture fill layers within the series of apertures erosion of the narrow mesa is attenuated. Finally, there is then chemical mechanical polish (CMP) planarized the blanket first aperture fill layer to form the series of patterned planarized first aperture fill layers within the series of apertures.
There is provided by the present invention a high density plasma chemical vapor deposition (HDP-CVD) method employed in conjunction with a chemical mechanical polish (CMP) planarizing method for forming within a topographic substrate layer employed within a microelectronics fabrication a series of patterned planarized aperture fill layers, where the series of patterned planarized aperture fill layers is formed with optimal uniformity and planarity and with attenuated topographic substrate layer damage. The method of the present invention realizes the foregoing objects by employing within the high density plasma chemical vapor deposition (HDP-CVD) method when forming a blanket planarized aperture fill layer from which is subsequently formed employing a chemical mechanical polish (CMP) planarizing method a series of patterned planarized aperture fill layers a deposition rate:sputtering rate ratio which provides a sufficient thickness of a protrusion of the blanket aperture fill layer upon a narrow mesa such that when chemical mechanical polish (CMP) planarizing the blanket aperture fill layer the series of patterned planarized aperture fill layers is formed with optimal uniformity and planarity and with attenuated topographic substrate layer damage.
The method of the present invention may be employed where the microelectronics fabrication is a semiconductor integrated circuit microelectronics fabrication, the topographic substrate layer is a semiconductor substrate employed within the semiconductor integrated circuit microelectronics fabrication, the series of apertures is a series of isolation trenches formed within the semiconductor substrate and the series of patterned planarized aperture fill layers is a series of patterned planarized trench isolation regions formed within the series of isolation trenches. The method of the present invention does not discriminate with respect to the nature of a microelectronics fabrication within which may be formed a series of patterned planarized aperture fill layers in accord with the method of the present invention. Thus, although the method of the present invention provides substantial value when forming a series of patterned planarized trench isolation regions within a series of isolation trenches within a semiconductor substrate employed within a semiconductor integrated circuit microelectronics fabrication, the method of the present invention may also be employed in forming a series of patterned planarized aperture fill layers including but not limited to patterned planarized aperture fill conductor layers, patterned planarized aperture fill semiconductor layers and patterned planarized aperture fill dielectric layers within trenches other than isolation trenches within substrates including but not limited to conductor substrates, semiconductor substrates, dielectric substrates and composites thereof employed within microelectronics fabrications including but not limited to semiconductor integrated circuit microelectronics fabrications solar cell microelectronics fabrications, ceramic substrate microelectronics fabrications and flat panel display microelectronics fabrications.
The method of the present invention is readily commercially implemented. The method of the present invention employs high density plasma chemical vapor deposition (HDP-CVD) methods in conjunction with chemical mechanical polish (CMP) planarizing methods as are generally known in the art of microelectronics fabrication. Since it is the process control within the method of the present invention which provides at least in part the method of the present invention, rather than the existence of the microelectronics fabrication methods which provides the present invention, the method of the present invention is readily commercially implemented.